1. Field of the invention
The present invention relates to an image sensor. More specifically, the present invention relates to an image sensor in which a number of photosensitive elements such as photodiodes arranged in a linear line are sequentially scanned and driven by a scanning type driving circuit which is constructed by a plurality of integrated circuits.
2. Description of the prior art
An apparatus utilizing an image sensor 10 as shown in FIG. 1 is provided with an LED array 12 which is accommodated in a housing 14 and illustratively irradiates a light onto an original document 16 which is moved below the LED array 12. The light from the LED array 12 is reflected on the original 16 which is relatively moved in a direction of an arrow mark 16a. A reflected light is focused by a short-focal lens array 18, entering a sensor array 20 which is formed on a substrate 22, that is, a photodiode array 24 in which a number of photodiodes PD are arranged in a linear line as shown in FIG. 2. On the substrate 22, as well seen from FIG. 2, a plurality of integrated circuits IC which constitute a scanning type driving circuit are mounted. Although not shown, a plurality of analog switches are included in respective ones of the integrated circuits IC, which are connected to individual photodiodes PD included in the photodiode array 24 by wires 26 one by one. In the respective integrated circuits IC, signal voltages which are outputted through the respective analog switches are withdrawn to a signal line 28. Each of the respective integrated circuits IC includes a shift register (not shown) which generates a drive pulse for sequentially turning the above described analog switches on or off. Then, a relay pulse is given from a shift register included in the integrated circuit at a preceding stage to a shift register included in the integrated circuit at a succeeding stage through a relay pulse line 30.
As shown in FIG. 3, an output of the sensor array 20 is given to a peak-holding circuit 34 through an amplifier 32. Therefore, a video signal a magnitude of which is dependent on an electric charge stored in each photodiode PD of the photodiode array 24 (FIG. 1 and FIG. 2) is outputted from the peak-holding circuit 34. In addition, a predetermined clock pulse is generated by a clock pulse generator 36 and the clock pulse is applied to the above described shift registers (not shown) included in the integrated circuits IC and to the peak-holding circuit 34.
The above described sensor array 20 is capable of being utilized in a facsimile, and in GIII facsimile, for example, it is required that a length of the photodiode array 24 (FIG. 2) is equal to a length of a shorter side of an A4 size, and it is required that a density of the photodiode array and a scanning rate thereof are 8 dots/mm and 10 milliseconds/line, respectively. However, an image sensor having a higher density and higher scanning rate is desired recently.
In an image sensor of a high density and a high scanning rate, an area of a light receiving portion of each photodiode PD (FIG. 2) included in the photodiode array 24 becomes small and a time for charging an electric charge in each photodiode also becomes short. Therefore, a signal outputted from such an image sensor becomes small in comparison with an image sensor of a low density and a low scanning rate. Therefore, in order to put an image sensor of a high density and a high scanning rate into practice, it is important to reduce a noise component which is superposed on a signal component.
A noise component can be roughly classified into two kinds of noise one of which is a switching noise generated in an analog switch which is incorporated in an integrated circuit and connected to a photosensitive element such as a photodiode and the other of which is a noise transferred from the shift register for sequentially driving the analog switch to a signal line.
One example of a method for reducing the former noise, that is, a switching noise of the analog switch is disclosed in, for example, Japanese Patent application Laid-open No. 35869/1985 laid-open on Feb. 23, 1985. An equivalent circuit of such an analog switch is shown in FIG. 4.
With reference to FIG. 4, in an analog switch SW, an N-channel MOS-FET 38n and a P-channel MOS-FET 38p which have the same gate capacitance are connected in parallel with each other. Then, a drive pulse which is given from a shift register (not shown) is applied to a gate of the N-channel MOS-FET 38n as it is, and the drive pulse is applied to a gate of the P-channel MOS-FET 38p through an inverter 40. Sources of the N-channel MOS-FET 38n and P-channel MOS-FET 38p are commonly connected to an anode of a photodiode PD included in the photodiode array 24 (FIG. 2), and a bias voltage from a bias voltage source 42 is applied to a cathode of the photodiode PD. The, drains of the N-channel MOS-FET 38n and the P-channel MOS-FET 38p are commonly connected to an output terminal Vo through a signal line 28 (FIG. 2). A load resistor 44 is connected in parallel with the output terminal Vo.
In FIG. 4 prior art, when the drive pulse is applied to the analog switch SW, the N-channel MOS-FET 38n is first turned-on, and the P-channel MOS-FET 38p is turned-on after a delay time due to the inverter 40. Therefore, the analog switch SW becomes conductive at this time so that an electric charge stored in the photodiode PD can flow into the load resistor 44 through the analog switch SW. Therefore, at the output terminal Vo, a terminal voltage generated on the load resistor 44 is withdrawn as a signal voltage.
As described above, in FIG. 4 prior art, a timing when the P-channel MOS-FET 38p is turned-on is shifted in time with respect to a timing when the N-channel MOS-FET 38n is turned on by the delay time of the inverter 40. In other words, the two MOS-FETs 38n and 38p cannot be simultaneously turned-on or -off. Therefore, if the drive pulse shown in FIG. 5 (A) is applied, a switching noise as shown in FIG. 5 (B) occurs in the analog switch SW. More specifically, although FIG. 4 prior art is intended to cancel the switching noise due to a gate-channel capacitance of a MOS-FET, such a switching noise has not been sufficiently reduced.
In addition, a method in which a positive switching noise and a negative switching noise are respectively integrated in an integration circuit and, by canceling the same, a switching noise is intended to be reduced is proposed in, for example, United State Pat. No. 4,301,477 issued on Nov. 17, 1981. However, since magnitudes of a switching noise in turning the two MOS-FETs 38n and 38p on and a switching noise in turning the same off are different from each other in FIG. 4 prior art, it is impossible to adopt a method proposed in United States Pat. No. 4,301,477 in FIG. 4 prior art. Therefore, FIG. 4 prior art is not an effective method for reducing a switching noise of an analog switch.